Freescale Semiconductor, Inc.
Resets
Table 5-1. Programmable COP Timeout Period Selection
Programmable COP Timeout Period
COP
CM1:CM0
f
= 4.0 MHz
= 2.0 MHz
f
= 3.5795 MHz
= 1.7897 MHz
f
= 2.0 MHz
= 1.0 MHz
f
= 1.0 MHz
= 0.5 MHz
Timeout Rate
OSC
OSC
OSC
OSC
f
f
f
f
OP
OP
OP
OP
15
00
01
10
11
16.38 ms
65.54 ms
262.14 ms
1.048 s
18.31 ms
73.24 ms
292.95 ms
1.172 s
32.77 ms
131.07 ms
524.29 ms
2.097 s
65.54 ms
262.14 ms
1.048 s
f
f
f
f
÷ 2
÷ 2
÷ 2
÷ 2
OP
OP
OP
OP
17
19
21
4.194 s
5.3.3.2 Non-Programmable COP Watchdog
A timeout of the 18-stage ripple counter in the non-programmable COP
watchdog generates a reset. The timeout period is 65.536 ms when
fOSC = 4 MHz. The timeout period for the non-programmable COP timer
is a direct function of the crystal frequency. The equation is:
262,144
Timeout period =
fOSC
Two memory locations control operation of the non-programmable COP
watchdog:
1. Non-programmable COP enable bit (NCOPE) in mask option
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See 9.5.3 Mask Option
Register 2.
NOTE: Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOPE bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
Technical Data
66
MC68HC705C8A — Rev. 3
Resets
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