Freescale Semiconductor, Inc.
Resets
Reset Sources
2. COP clear bit (COPC) at address $1FF0
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that location. See 9.5.2 Mask Option Register 1.
NOTE: The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
Figure 5-4 is a diagram of the non-programmable COP.
NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE)
NCOPE
÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2
÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2
Figure 5-4. Non-Programmable COP Watchdog Diagram
5.3.4 Clock Monitor Reset
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the internal bus clock for a certain period of time.
The timeout period depends on processing parameters and varies from
5 µs to 100 µs, which implies that systems using a bus clock rate of
200 kHz or less should not use the clock monitor function.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consideration is required when using the STOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Resets
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