Freescale Semiconductor, Inc.
Resets
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
U
6
5
4
3
2
1
Bit 0
U
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 5-2. Programmable COP Reset Register (COPRST)
The programmable COP control register (COPCR) shown in Figure 5-3
does these functions:
• Flags programmable COP watchdog resets
• Enables the clock monitor
• Enables the programmable COP watchdog
• Controls the timeout period of the programmable COP watchdog
Address: $001E
Bit 7
0
6
0
5
0
4
3
2
1
Bit 0
CM0
Read:
Write:
Reset:
COPF
CME
PCOPE
CM1
0
0
0
U
0
0
0
0
= Unimplemented
U = Unaffected
Figure 5-3. Programmable COP Control Register (COPCR)
COPF — COP Flag
This read-only bit is set when a timeout of the programmable COP
watchdog occurs or when the clock monitor detects a slow or absent
internal clock. Clear the COPF bit by reading the COP control register.
Reset has no effect on the COPF bit.
1 = COP timeout or internal clock failure
0 = No COP timeout and no internal clock failure
Technical Data
64
MC68HC705C8A — Rev. 3
Resets
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