Freescale Semiconductor, Inc.
Resets
Reset Sources
5.3.3.1 Programmable COP Watchdog Reset
A timeout of the 18-stage ripple counter in the programmable COP
watchdog generates a reset. Figure 5-1 is a diagram of the
programmable COP watchdog. Two registers control and monitor
operation of the programmable COP watchdog:
• COP reset register (COPRST), $001D
• COP control register (COPCR), $001E
To clear the programmable COP watchdog and begin a new timeout
period, write these values to the COP reset register (COPRST).
See Figure 5-2.
1. $55
2. $AA
The $55 write must precede the $AA write. Instructions may be executed
between the write operations provided that the COP watchdog does not
time out before the second write.
PROGRAMMABLE COP WATCHDOG (MC68HC705C8 TYPE)
INTERNAL
CLOCK
÷4
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
(fOP
)
213
CM0
CM1
215
217
219
221
RESET
PCOPE
÷ 4
÷ 2 ÷ 2
÷ 2 ÷ 2
÷ 2 ÷ 2
COPRST
Figure 5-1. Programmable COP Watchdog Diagram
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Resets
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