Freescale Semiconductor, Inc.
MC68HSC705C8A
A.7 5.0-Volt High-Speed SPI Timing
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
Operating frequency
(1)
Number
f
f
Master
Slave
dc
dc
0.5
4.0
OP(S)
OP
f
MHz
OP(S)
Cycle time
Master
t
t
1
2
3
4
5
6
7
2.0
250
—
—
CYC(M)
CYC
Slave
t
ns
CYC(S)
Enable lead time
Master
(3)
t
—
—
ns
Lead(M)
Note
125
Slave
t
Lead(S)
Enable lag time
Master
(2)
t
—
—
ns
ns
ns
ns
ns
Lag(M)
Note
375
Slave
t
Lag(S)
Clock (SCK) high time
Master
t
170
95
—
—
W(SCKH)M
Slave
t
W(SCKH)S
Clock (SCK) low time
Master
t
170
95
—
—
W(SCKL)M
Slave
t
W(SCKL)S
Data setup time (inputs)
t
Master
Slave
50
50
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
t
Master
Slave
50
50
—
—
H(M)
t
H(S)
(4)
Access time
t
8
9
0
60
ns
ns
A
Slave
(5)
Disable time
t
—
120
DIS
Slave
Data valid time
t
Master (before capture edge)
t
10
0.25
—
—
120
V(M)
CYC(M)
(6)
t
ns
Slave (after enable edge)
V(S)
Continued
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
