Freescale Semiconductor, Inc.
MC68HSC705C8A
Table A-1. Programmable COP Timeout Period Selection
Programmable COP Timeout Period
COP
CM1:CM0
Timeout
Rate
f
= 8.0 MHz
= 4.0 MHz
f
= 4.0 MHz
= 2.0 MHz
f
= 3.5795 MHz
= 1.7897 MHz
f
OSC
= 2.0 MHz
= 1.0 MHz
OSC
OSC
OSC
f
f
f
f
OP
OP
OP
OP
15
00
01
10
11
8.192 ms
32.77 ms
131.07 ms
524.29 ms
16.38 ms
65.54 ms
262.14 ms
1.048 s
18.31 ms
73.24 ms
292.95 ms
1.172 s
32.77 ms
131.07 ms
524.29 ms
2.097 s
f
÷ 2
÷ 2
÷ 2
OP
OP
OP
17
19
f
f
21
f
÷ ÷2
OP
A.3 5.0-Volt High-Speed DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output high voltage
I
I
I
= –0.8 mA
Load
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –1.6 mA
—
—
—
—
—
—
V
V
– 0.8
DD
V
Load
OH
PD4–PD1
= –5.0 mA
Load
PC7
Output low voltage
I
I
= 1.6 mA
Load
V
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 20 mA
—
—
—
—
0.4
0.4
V
OL
Load
PC7
(3)
Supply current
(4)
Run
—
—
5.92
2.27
14
7.0
mA
mA
(5)
Wait
I
DD
(6)
Stop
—
—
5
2.0
50
50
µA
µA
25°C
–40°C to +85°C
1. V = 5 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 8.0 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run I
.
DD
5. Wait I measured using external square wave clock source (f
= 8.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I
.
DD
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V, V = V – 0.2 V.
DD
DD
IL
IH
DD
Technical Data
202
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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