Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI — SPI Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI enabled
0 = SPI disabled
MSTR — Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
SPR1 and SPR0 — SPI Clock Rate Bits
These read/write bits select the master mode serial clock rate, as
shown in Table 11-1. The SPR1 and SPR0 bits of a slave SPI have
no effect on the serial clock. Reset has no effect on SPR1 and SPR0.
Table 11-1. SPI Clock Rate Selection
SPR[1:0]
SPI Clock Rate
Internal Clock ÷ 2
Internal Clock ÷ 4
Internal Clock ÷ 16
Internal Clock ÷ 32
00
01
10
11
Technical Data
150
MC68HC705C8A — Rev. 3
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
