Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.3 SPI Status Register
The SPSR shown in Figure 11-9 contains flags to signal these
conditions:
• SPI transmission complete
• Write collision
• Mode fault
Address: $000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SPIF
WCOL
MODF
0
0
0
= Unimplemented
Figure 11-9. SPI Status Register (SPSR)
SPIF — SPI Flag
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
1 = Transmission complete
0 = Transmission not complete
WCOL — Write Collision Bit
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
1 = Invalid write to SPDR
0 = No invalid write to SPDR
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Peripheral Interface (SPI)
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