Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
16.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 16-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ1 latch.
• Reset — A reset automatically clears both interrupt latches.
ACK1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQ1F
CLR
D
Q
SYNCHRO-
NIZER
IRQ1
INTERRUPT
REQUEST
CK
IRQ1
IRQ
LATCH
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 16-1. IRQ Block Diagram
Technical Data
MC68HC908AS60 — Rev. 1.0
External Interrupt Module (IRQ)
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