Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
16.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1
interrupt latch can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. See 9.8.3 SIM Break Flag Control
Register.
To allow software to clear the IRQ1 latch during a break interrupt, write
a logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
16.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
• Shows the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001A
Bit 7
0
6
5
0
4
0
3
IRQF1
R
2
0
1
Bit 0
Read:
Write:
Reset:
0
IMASK1 MODE1
R
R
R
0
R
0
ACK1
0
0
0
0
0
0
R
=Reserved
Figure 16-4. IRQ Status and Control Register (ISCR)
Technical Data
MC68HC908AS60 — Rev. 1.0
External Interrupt Module (IRQ)
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