Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI) Module
15.4.3 False Reset Protection
The VDD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, VDD must
remain at or below the LVITRIPF level for nine or more consecutive CPU
cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the
MCU out of reset.
15.5 LVI Status Register
The LVI status register (LVISR) flags VDD voltages below the LVITRIPF
level.
Address: $FE0F
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
LVITRIPF voltage for 32 to 40 CGMXCLK cycles. See Table 15-1.
Reset clears the LVIOUT bit.
Table 15-1. LVIOUT Bit Indication
V
DD
LVIOUT
For Number of
CGMXCLK Cycles:
At Level:
V
V
> LVI
Any
0
0
DD
TRIPR
< LVI
< LVI
< LVI
< 32 CGMXCLK cycles
DD
DD
DD
TRIPF
TRIPF
Between 32 and 40
CGMXCLK Ccycles
V
V
0 or 1
> 40 CGMXCLK cycles
Any
1
TRIPF
LVI
TRIPF
< V
< LVI
Previous value
DD
TRIPR
Technical Data
MC68HC908AS60 — Rev. 1.0
Low-Voltage Inhibit (LVI) Module
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