Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI) Module
LVI Interrupts
15.6 LVI Interrupts
The LVI module does not generate interrupt requests.
15.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
15.7.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
15.7.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip must bypass the digital filter to generate a reset and bring the MCU
out of stop.
With the LVIPWR bit in the configuration register programmed to logic 1
and the LVISTOP bit at a logic 0, the LVI module will be inactive after a
STOP instruction.
MC68HC908AS60 — Rev. 1.0
Technical Data
Low-Voltage Inhibit (LVI) Module
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