Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
Functional Description
Addr.
Register Name
Bit 7
0
6
5
0
4
0
3
IRQF1
R
2
0
1
Bit 0
Read:
0
IRQ Status and Control
IMASK1 MODE1
$001A
Register (ISCR) Write:
See page 220.
R
R
R
0
R
0
ACK1
0
Reset:
0
0
0
0
0
R
=Reserved
Figure 16-2. IRQ I/O Register Summary
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE1
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 16-3.)
MC68HC908AS60 — Rev. 1.0
Technical Data
External Interrupt Module (IRQ)
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