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MC68HC908AP64CFB 参数 Datasheet PDF下载

MC68HC908AP64CFB图片预览
型号: MC68HC908AP64CFB
PDF下载: 下载PDF文件 查看货源
内容描述: [MC68HC908AP64CFB]
分类和应用: 外围集成电路时钟
文件页数/大小: 325 页 / 1651 K
品牌: FREESCALE [ Freescale ]
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Infrared Serial Communications Interface Module (IRSCI)  
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit  
character with no errors is  
154 147  
× 100 = 4.54%  
-------------------------  
154  
For a 9-bit character, data sampling of the stop bit takes the receiver  
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.  
With the misaligned character shown in Figure 12-10, the receiver counts 170 RT cycles at the point when  
the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.  
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit  
character with no errors is  
170 163  
× 100 = 4.12%  
-------------------------  
170  
Fast Data Tolerance  
Figure 12-11 shows how much a fast received character can be misaligned without causing a noise error  
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data  
samples at RT8, RT9, and RT10.  
STOP  
IDLE OR NEXT CHARACTER  
RECEIVER  
RT CLOCK  
DATA  
SAMPLES  
Figure 12-11. Fast Data  
For an 8-bit character, data sampling of the stop bit takes the receiver  
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.  
With the misaligned character shown in Figure 12-11, the receiver counts 154 RT cycles at the point when  
the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles.  
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit  
character with no errors is  
154 160  
-------------------------  
154  
˙
× 100 = 3.90%  
For a 9-bit character, data sampling of the stop bit takes the receiver  
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.  
With the misaligned character shown in Figure 12-11, the receiver counts 170 RT cycles at the point when  
the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles.  
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit  
character with no errors is  
MC68HC908AP Family Data Sheet, Rev. 4  
194  
Freescale Semiconductor  
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