Infrared Serial Communications Interface Module (IRSCI)
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Framing error (FE) — The FE bit in IRSCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in IRSCC3 enables FE to generate SCI error
CPU interrupt requests.
Parity error (PE) — The PE bit in IRSCS1 is set when the SCI detects a parity error in incoming
data. The parity error interrupt enable bit, PEIE, in IRSCC3 enables PE to generate SCI error CPU
interrupt requests.
12.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
12.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to 7.6 Low-Power Modes for information on exiting wait mode.
12.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to 7.6 Low-Power Modes for information on exiting stop mode.
12.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a two-step read/write clearing procedure. If software does the first step on such a
bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
12.8 I/O Signals
The two IRSCI I/O pins are:
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PTC6/SCTxD — Transmit data
PTC7/SCRxD — Receive data
MC68HC908AP Family Data Sheet, Rev. 4
196
Freescale Semiconductor
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