SCI Functional Description
170 – 176
-------------------------
170
× 100 = 3.53%
12.5.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in IRSCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in IRSCC1, either of two conditions on the RxD pin can bring the
receiver out of the standby state:
•
Address mark — An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start
bit or after the stop bit.
NOTE
Clearing the WAKE bit after the RxD pin has been idle may cause the
receiver to wake up immediately.
12.5.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
•
SCI receiver full (SCRF) — The SCRF bit in IRSCS1 indicates that the receive shift register has
transferred a character to the IRSCDR. SCRF can generate a receiver interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in IRSCC2 enables the SCRF bit to generate receiver
CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in IRSCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the RxD pin. The idle line interrupt enable bit, ILIE, in IRSCC2 enables the IDLE bit to
generate CPU interrupt requests.
12.5.3.8 Error Interrupts
The following receiver error flags in IRSCS1 can generate CPU interrupt requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the IRSCDR. The previous character
remains in the IRSCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in
IRSCC3 enables OR to generate SCI error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in
IRSCC3 enables NF to generate SCI error CPU interrupt requests.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
195
FREESCALE [ Freescale ]
