Freescale Semiconductor, Inc.
Parallel Input/Output
4.5.2 DDRC — Data direction register for port C
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data direction C (DDRC)
$0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000
DDC[7:0] — Data direction for port C
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.6 Port D
Port D is a 6-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port D pins are shared with
SCI and SPI functions, as shown in the following table.
Alternate
Pin
function
PD0
PD1
RXD1
TXD1
See Serial
Communications Interface
(SCI) for more information.
PD2
PD3
PD4
PD5
MISO
MOSI
SCK
SS
See Serial Peripheral
Interface (SPI) for more
information.
On reset the pins are configured as general purpose high-impedance
inputs.
4.6.1 PORTD — Port D data register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port D data (PORTD)
$0008 PD5 PD4 PD3 PD2 PD1 PD0 undefined
0
0
This is a read/write register and is not affected by reset. The bits may be
read and written at any time, but, when a pin is allocated to its alternate
Technical Data
MC68HC11P2 — Rev 1.0
Parallel Input/Output
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