Freescale Semiconductor, Inc.
Parallel Input/Output
4.9.1 PORTG — Port G data register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port G data (PORTG)
$007E PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.9.2 DDRG — Data direction register for port G
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data direction G (DDRG)
$007F DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
DDG[7:0] — Data direction for port G
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.10 Port H
Port H is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port H pins are shared with
SCI/MI BUS and PWM functions, as shown in the following table.
Alternate
function
Pin
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PW1
PW2
See Timing System
for more information.
PW3
PW4
RXD2
TXD2
RXD3
TXD3
See Serial Communications
Interface (SCI) and Motorola
Interconnect Bus (MI BUS)
for more information.
On reset the pins are configured as general purpose high-impedance
Technical Data
MC68HC11P2 — Rev 1.0
Parallel Input/Output
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