Freescale Semiconductor, Inc.
Parallel Input/Output
Port G
4.8.1 PORTF — Port F data register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port F data (PORTF)
$0005 PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.8.2 DDRF — Data direction register for port F
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data direction F (DDRF)
$0003 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000
DDF[7:0] — Data direction for port F
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.9 Port G
Port G is an 8-bit bidirectional port, with both data and data direction
registers. In addition to its I/O capability, port G pin 7 (PG7) is used as
the R/W pin in expanded and test modes.
The state of PG7 on reset is mode dependent. In single chip or bootstrap
mode, PG7 is a high-impedance input. In expanded or test modes, PG7
is the R/W output. The remaining pins (PG[6:0]) are high-impedance
inputs, with software selectable internal pull-up resistors (see Internal
pull-up/pull-down resistors).
MC68HC11P2 — Rev 1.0
Technical Data
Parallel Input/Output
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