Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
4.3.1 PORTA — Port A data register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port A data (PORTA)
$0000 PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0 undefined
This is a read/write register and is not affected by reset. The bits may be
read and written at any time, but, when a pin is allocated to its alternate
function, a write to the corresponding register bit has no affect on the pin
state.
4.3.2 DDRA — Data direction register for port A
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
Data direction A (DDRA)
$0001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000
DDA[7:0] — Data direction for port A
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.4 Port B
Port B is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port B pins are used as the
nonmultiplexed high order address pins, as shown in the following
table.
Alternate
Pin
function
PB0
PB1
PB2
PB3
PB4
PB5
PB6
A8
A9
In expanded or test
mode, the pins
become the high
order address and
port B is not
A10
A11
A12
A13
A14
included in the
memory map.
MC68HC11P2 — Rev 1.0
Technical Data
Parallel Input/Output
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