Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
can resume. Refer to CPU Core and Instruction Set for further
information.
Table 10-5. Stacking order on entry to interrupts
Memory location
SP
CPU registers
PCL
SP – 1
PCH
SP – 2
IYL
SP – 3
IYH
SP – 4
IXL
SP – 5
IXH
SP – 6
ACCA
ACCB
CCR
SP – 7
SP – 8
10.6.2 Nonmaskable interrupt request (XIRQ)
Nonmaskable interrupts are useful because they can always interrupt
CPU operations. The most common use for such an interrupt is for
serious system problems, such as program runaway or power failure.
The XIRQ input is an updated version of the NMI (nonmaskable
interrupt) input of earlier MCUs.
Upon reset, both the X-bit and I-bit of the CCR are set to inhibit all
maskable interrupts and XIRQ. After minimum system initialization,
software can clear the X-bit by a TAP instruction, enabling XIRQ
interrupts. Thereafter, software cannot set the X-bit. Thus, an XIRQ
interrupt is a nonmaskable interrupt. Because the operation of the I-bit-
related interrupt structure has no effect on the X-bit, the internal XIRQ
pin remains unmasked. In the interrupt priority logic, the XIRQ interrupt
has a higher priority than any source that is maskable by the I-bit. All I-
bit-related interrupts operate normally with their own priority relationship.
When an I-bit-related interrupt occurs, the I-bit is automatically set by
hardware after stacking the CCR byte. The X-bit is not affected. When
an X-bit-related interrupt occurs, both the X and I bits are automatically
MC68HC11P2 — Rev 1.0
Technical Data
Resets and Interrupts
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