Freescale Semiconductor, Inc.
Resets and Interrupts
Reset and interrupt priority
Table 10-4. Interrupt and reset vector assignments
CCR
mask bit mask
Local
Vector address
FFC0, C1 – FFD0, D1 reserved
Interrupt source
—
—
• SCI/MI BUS3 receive data register full
• SCI/MI BUS3 receiver overrun
• SCI3 transmit data register empty
• SCI3 transmit complete
RIE3
RIE3
TIE3
TCIE3
ILIE3
FFD2, D3
FFD4, D5
FFD6, D7
I
• SCI3 idle line detect
• SCI/MI BUS2 receive data register full
• SCI/MI BUS2 receiver overrun
• SCI2 transmit data register empty
• SCI2 transmit complete
RIE2
RIE2
TIE2
TCIE2
ILIE2
I
I
• SCI2 idle line detect
• SCI1 receive data register full
• SCI1 receiver overrun
• SCI1 transmit data register empty
• SCI1 transmit complete
• SCI1 idle line detect
RIE
RIE
TIE
TCIE
ILIE
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
SPI serial transfer complete
Pulse accumulator input edge
Pulse accumulator overflow
Timer overflow
I
SPIE
PAII
I
I
PAOVI
TOI
I
Timer input capture 4/output compare 5
Timer output compare 4
Timer output compare 3
Timer output compare 2
Timer output compare 1
Timer input capture 3
Timer input capture 2
Timer input capture 1
Real-time interrupt
IRQ pin
I
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
I
I
I
I
I
I
IC2I
I
IC1I
I
I
RTII
None
None
None
None
XIRQ pin
X
Software interrupt
None
None
Illegal opcode trap
COP failure
None NOCOP
Clock monitor fail
None
None
CME
None
RESET
MC68HC11P2 — Rev 1.0
Technical Data
Resets and Interrupts
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