Freescale Semiconductor, Inc.
Resets and Interrupts
Reset and interrupt priority
10.5.1 HPRIO — Highest priority I-bit interrupt and misc. register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RBOO
Highest priority interrupt (HPRIO) $003C
SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
T
RBOOT, SMOD, and MDA bits depend on power-up initialization mode
and can only be written in special modes when SMOD = 1. Refer to
Table 3-4.
RBOOT — Read bootstrap ROM (refer to Operating Modes and On-
Chip Memory)
1 = Bootloader ROM enabled, at $BE40–$BFFF.
0 = Bootloader ROM disabled and not in map.
SMOD — Special mode select (refer to Operating Modes and On-Chip
Memory)
1 = Special mode variation in effect.
0 = Normal mode variation in effect.
MDA — Mode select A (refer to Operating Modes and On-Chip
Memory)
1 = Normal expanded or special test mode in effect.
0 = Normal single chip or special bootstrap mode in effect.
PSEL[4:0] — Priority select bits
These bits select one interrupt source to be elevated above all other
I-bit-related sources and can be written to only while the I-bit in the
CCR is set (interrupts disabled). See Table 10-3.
MC68HC11P2 — Rev 1.0
Technical Data
Resets and Interrupts
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