CPM Electrical Characteristics
Table 24. Ethernet Timing (continued)
Characteristic
All
Frequencies
Num
Unit
Min
Max
133 TENA active delay (from TCLK3 rising edge)
134 TENA inactive delay (from TCLK3 rising edge)
138 CLKO1 low to SDACK asserted 2
10
10
—
—
50
50
20
20
ns
ns
ns
ns
139 CLKO1 low to SDACK negated 2
1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.
2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 55. Ethernet Collision Timing Diagram
RCLK3
121
121
124
123
Last Bit
RxD3
(Input)
125
126
127
RENA(CD3)
(Input)
Figure 56. Ethernet Receive Timing Diagram
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
60
Freescale Semiconductor
FREESCALE [ Freescale ]
