CPM Electrical Characteristics
TCLK3
102
102
101
100
TxD3
(Output)
103
RTS3
(Output)
104
107
104
105
CTS3
(Echo Input)
Figure 54. HDLC Bus Timing Diagram
13.7 Ethernet Electrical Specifications
Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.
Table 24. Ethernet Timing
All
Frequencies
Num
Characteristic
Unit
Min
Max
120 CLSN width high
121 RCLK3 rise/fall time
122 RCLK3 width low
123 RCLK3 clock period 1
124 RXD3 setup time
125 RXD3 hold time
40
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
80
20
5
120
—
—
126 RENA active delay (from RCLK3 rising edge of the last data bit)
127 RENA width low
10
100
—
—
—
128 TCLK3 rise/fall time
15
—
129 TCLK3 width low
40
99
—
130 TCLK3 clock period1
101
50
50
131 TXD3 active delay (from TCLK3 rising edge)
132 TXD3 inactive delay (from TCLK3 rising edge)
6.5
MPC875/MPC870 Hardware Specifications, Rev. 3.0
59
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
