欢迎访问ic37.com |
会员登录 免费注册
发布采购

KMPC875ZT133 参数 Datasheet PDF下载

KMPC875ZT133图片预览
型号: KMPC875ZT133
PDF下载: 下载PDF文件 查看货源
内容描述: 硬件规格 [Hardware Specifications]
分类和应用:
文件页数/大小: 84 页 / 1372 K
品牌: FREESCALE [ Freescale ]
 浏览型号KMPC875ZT133的Datasheet PDF文件第33页浏览型号KMPC875ZT133的Datasheet PDF文件第34页浏览型号KMPC875ZT133的Datasheet PDF文件第35页浏览型号KMPC875ZT133的Datasheet PDF文件第36页浏览型号KMPC875ZT133的Datasheet PDF文件第38页浏览型号KMPC875ZT133的Datasheet PDF文件第39页浏览型号KMPC875ZT133的Datasheet PDF文件第40页浏览型号KMPC875ZT133的Datasheet PDF文件第41页  
Bus Signal Timing  
Table 12 shows the PCMCIA timing for the MPC875/870.  
Table 12. PCMCIA Timing  
33 MHz 40 MHz  
66 MHz  
80 MHz  
Num  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
A(0:31), REG valid to PCMCIA  
20.70  
16.70  
9.40  
7.40  
ns  
P44 strobe asserted 1  
(MIN = 0.75 × B1 – 2.00)  
A(0:31), REG valid to ALE  
28.30  
23.00  
13.20  
10.50  
ns  
P45 negation1  
(MIN = 1.00 × B1 – 2.00)  
CLKOUT to REG valid  
(MAX = 0.25 × B1 + 8.00)  
7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13  
ns  
ns  
ns  
ns  
ns  
P46  
P47  
P48  
P49  
CLKOUT to REG invalid  
(MIN = 0.25 × B1 + 1.00)  
8.60  
7.30  
4.80  
4.125  
CLKOUT to CE1, CE2 asserted  
(MAX = 0.25 × B1 + 8.00)  
7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13  
7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13  
CLKOUT to CE1, CE2 negated  
(MAX = 0.25 × B1 + 8.00)  
CLKOUT to PCOE, IORD, PCWE,  
11.00  
11.00  
11.00  
11.00  
P50 IOWR assert time (MAX =  
0.00 × B1 + 11.00)  
CLKOUT to PCOE, IORD, PCWE, 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00  
ns  
P51 IOWR negate time (MAX =  
0.00 × B1 + 11.00)  
CLKOUT to ALE assert time (MAX 7.60 13.80 6.30 12.50 3.80 10.00 3.13  
= 0.25 × B1 + 6.30)  
9.40  
11.13  
ns  
ns  
ns  
ns  
P52  
P53  
P54  
CLKOUT to ALE negate time (MAX  
= 0.25 × B1 + 8.00)  
15.60  
14.30  
11.80  
PCWE, IOWR negated to D(0:31)  
5.60  
8.00  
4.30  
8.00  
1.80  
8.00  
1.125  
8.00  
invalid1(MIN – = 0.25 × B1 – 2.00)  
WAITA and WAITB valid to  
P55 CLKOUT rising edge1  
(MIN = 0.00 × B1 + 8.00)  
CLKOUT rising edge to WAITA and 2.00  
P56 WAITB invalid1 (MIN = 0.00 × B1 +  
2.00)  
2.00  
2.00  
2.00  
ns  
1 PSST = 1. Otherwise add PSST times cycle time.  
PSHT = 0. Otherwise add PSHT times cycle time.  
These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA  
current cycle. The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.  
See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.  
MPC875/MPC870 Hardware Specifications, Rev. 3.0  
37  
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE  
Freescale Semiconductor  
 复制成功!