Bus Signal Timing
Figure 21 provides the timing for the synchronous external master access controlled by the GPCM.
CLKOUT
B41
B40
B42
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 23 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 23. Asynchronous External Master—Control Signals Negation Timing
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
35
Freescale Semiconductor
FREESCALE [ Freescale ]
