Bus Signal Timing
Table 11 provides the interrupt timing for the MPC875/870.
Table 11. Interrupt Timing
All Frequencies
Min Max
Num
Characteristic 1
Unit
I39
I40
I41
I42
I43
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
6.00
2.00
3.00
3.00
ns
ns
ns
ns
—
IRQx pulse width high
IRQx edge-to-edge time
4xTCLOCKOUT
1 The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC875/870 is able to support.
Figure 24 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 24. Interrupt Detection Timing for External Level Sensitive Lines
Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I41
I42
IRQx
I43
I43
Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
36
Freescale Semiconductor
FREESCALE [ Freescale ]
