Bus Signal Timing
Table 14 shows the debug port timing for the MPC875/870.
Table 14. Debug Port Timing
All Frequencies
Min
Num
Characteristic
Unit
Max
D61 DSCK cycle time
3 × TCLOCKOUT
—
—
ns
ns
ns
D62 DSCK clock pulse width
D63 DSCK rise and fall times
D64 DSDI input data setup time
D65 DSDI data hold time
1.25 × TCLOCKOUT
0.00
8.00
5.00
0.00
0.00
3.00
D66 DSCK low to DSDO data valid
D67 DSCK low to DSDO invalid
15.00 ns
2.00 ns
Figure 31 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
Figure 31. Debug Port Clock Input Timing
Figure 32 provides the timing for the debug port.
D63
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 32. Debug Port Timings
MPC875/MPC870 Hardware Specifications, Rev. 3.0
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
