Serial Host Interface SPI Protocol Timing
HOREQ
(Output)
343
342
342
318
317
HACK
(Input)
RXH
Read
327
326
328
329
H0-H7
(Output)
Data
Valid
Figure 3-26 Host DMA Read Timing Diagram
3.12 Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing
Filter
Mode
No.
Characteristics1
Mode
Expression2
Min
Max
Unit
140 Tolerable spike width on clock or data in
—
Bypassed
Narrow
Wide
—
—
—
—
—
—
0
ns
50
100
141 Minimum serial clock cycle = tSPICC(min) Master Bypassed
6 × TC+46
6 × TC+152
6 × TC+223
86.2
192.2
263.2
—
—
—
ns
ns
ns
ns
ns
Narrow
Wide
142 Serial clock high period
Master Bypassed
Narrow
0.5 × tSPICC –10
0.5 × tSPICC –10
0.5 × tSPICC –10
38
91
—
—
—
Wide
126.5
Slave
Bypassed
2.5 × TC + 12
2.5 × TC + 102
2.5 × TC + 189
28.8
118.8
205.8
—
—
—
Narrow
Wide
143 Serial clock low period
Master Bypassed
Narrow
0.5 × tSPICC –10
0.5 × tSPICC –10
0.5 × tSPICC –10
38
—
Wide
Slave
Bypassed
Narrow
Wide
2.5 × TC + 12
2.5 × TC + 102
2.5 × TC + 189
28.8
118.8
205.8
—
—
—
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-37
FREESCALE [ Freescale ]
