Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing (Continued)
No.
Characteristics1, 2, 3
Symbol
Expression3
Min
Max Condition4 Unit
78 SCKT rising edge to FST out (bl) high
79 SCKT rising edge to FST out (bl) low
80 SCKT rising edge to FST out (wr) high6
82 SCKT rising edge to FST out (wr) low6
83 SCKT rising edge to FST out (wl) high
84 SCKT rising edge to FST out (wl) low
—
—
—
—
29.0
15.0
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31.0
17.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
—
—
33.0
19.0
x ck
i ck
—
—
30.0
16.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
85 SCKT rising edge to data out enable from
high impedance
—
—
31.0
17.0
x ck
i ck
86 SCKT rising edge to transmitter #0 drive
enable assertion
—
—
34.0
20.0
x ck
i ck
87 SCKT rising edge to data out valid
—
—
26.5
21.0
x ck
i ck
88 SCKT rising edge to data out high
impedance7
—
—
31.0
16.0
x ck
i ck
89 SCKT rising edge to transmitter #0 drive
enable deassertion7
—
—
34.0
20.0
x ck
i ck
90 FST input (bl, wr) setup time before SCKT
falling edge6
2.0
—
—
x ck
i ck
21.0
91 FST input (wl) to data out enable from high
impedance
—
—
—
—
—
—
—
27.0
—
ns
ns
ns
92 FST input (wl) to transmitter #0 drive enable
assertion
—
31.0
—
93 FST input (wl) setup time before SCKT falling
edge
2.0
—
—
x ck
i ck
21.0
94 FST input hold time after SCKT falling edge
—
—
—
—
4.0
0.0
—
—
x ck
i ck
ns
ns
95 Flag output valid after SCKT rising edge
—
—
32.0
18.0
x ck
i ck
96 HCKR/HCKT clock cycle
—
—
—
2 x TC
—
40.0
—
—
ns
ns
ns
97 HCKT input rising edge to SCKT output
98 HCKR input rising edge to SCKR output
18.0
18.0
—
—
Freescale Semiconductor
DSP56371 Technical Data
47