Serial Host Interface (SHI) I2C Protocol Timing
13.1
Programming the Serial Clock
2
The programmed serial clock cycle, TI CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control
register).
2
The expression for TI CCP is
TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
where
—
HRS is the pre-scaler rate select bit. When HRS is cleared, the fixed
divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed.
—
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 × TC
(if HDM[7:0] = $02 and HRS = 1)
to
4096 × TC (if HDM[7:0] = $FF and HRS = 0)
2
The programmed serial clock cycle (TI CCP), SCL rise time (TR), should be chosen in order to achieve the desired SCL serial
clock cycle (TSCL), as shown in Table 22.
44
46
49
48
SCL
SDA
50
53
51
45
52
MSB
LSB
ACK
Stop
Stop
Start
47
60
58
55
56
59
61
57
HREQ
2
Figure 13. I C Timing
Freescale Semiconductor
DSP56371 Technical Data
45
FREESCALE [ Freescale ]
