Serial Host Interface (SHI) I2C Protocol Timing
2
13
Serial Host Interface (SHI) I C Protocol Timing
2
Table 21. SHI I C Protocol Timing
Standard I2C*
Standard
Fast-Mode
Unit
Symbol/
No.
Characteristics1
SCL clock frequency
Expression
Min
—
Max
100
—
—
—
—
—
—
5
Min
—
Max
400
—
—
—
—
—
—
5
44
44
45
46
47
48
49
50
51
52
53
54
55
56
57
FSCL
TSCL
kHz
µs
SCL clock cycle
10
2.5
1.3
0.6
0.6
1.3
1.3
—
Bus free time
TBUF
4.7
4.7
4.0
4.7
4.0
—
µs
Start condition set-up time
Start condition hold time
SCL low period
TSUSTA
THD;STA
TLOW
µs
µs
µs
SCL high period
THIGH
µs
SCL and SDA rise time
SCL and SDA fall time
Data set-up time
T
ns
R
T
F
—
5
—
5
ns
TSU;DAT
THD;DAT
FOSC
250
0.0
10.6
—
—
—
—
3.4
—
—
100
0.0
28.5
—
—
0.9
—
0.9
—
—
ns
Data hold time
µs
DSP clock frequency
SCL low to data out valid
Stop condition setup time
MHz
µs
TVD;DAT
TSU;STO
tSU;RQI
4.0
0.0
0.6
0.0
µs
HREQ in deassertion to last SCL edge (HREQ
in set-up time)
ns
58
First SCL sampling edge to HREQ output
deassertion
TNG;RQO
4 × TC + 30
TAS;RQO
—
—
—
—
—
—
ns
ns
59
60
Last SCL edge to HREQ output not deasserted
HREQ in assertion to first SCL edge
2 × TC + 30
TAS;RQI
50
50
0.5 × TI2CCP
-0.5 × TC - 21
4327
0.0
—
—
927
0.0
—
—
ns
ns
61
First SCL edge to HREQ in not asserted
(HREQ in hold time.)
tHO;RQI
Note:
1. VCORE_VDD = 1.2 5 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
44
DSP56371 Technical Data
Freescale Semiconductor
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