Enhanced Serial Audio Interface Timing
14
Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing
No.
62 Clock cycle5
Characteristics1, 2, 3
Symbol
Expression3
Min
22.3
22.3
Max Condition4 Unit
tSSICC
4 × T
—
—
—
i ck
x ck
x ck
ns
c
4 × T
c
SCKT:max[(3*TC) or t87] 26.5
63 Clock high period
• For internal clock
• For external clock
64 Clock low period
—
—
2 × T − 10.0
3.4
—
—
ns
ns
c
2 × T
10.0
c
• For internal clock
2 × T − 10.0
3.4
—
—
c
• For external clock
2 × T
10.0
c
65 SCKR rising edge to FSR out (bl) high
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
37.0
22.0
x ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i ck a
66 SCKR rising edge to FSR out (bl) low
67 SCKR rising edge to FSR out (wr) high6
68 SCKR rising edge to FSR out (wr) low6
69 SCKR rising edge to FSR out (wl) high
70 SCKR rising edge to FSR out (wl) low
—
—
—
—
—
—
—
—
—
—
—
—
—
—
37.0
22.0
x ck
i ck a
—
—
39.0
24.0
x ck
i ck a
—
—
39.0
24.0
x ck
i ck a
—
—
36.0
21.0
x ck
i ck a
—
—
37.0
22.0
x ck
i ck a
71 Data in setup time before SCKR (SCK in
synchronous mode) falling edge
0.0
—
—
x ck
i ck
19.0
72 Data in hold time after SCKR falling edge
5.0
3.0
—
—
x ck
i ck
73 FSR input (bl, wr) high before SCKR falling
edge 6
1.0
—
—
x ck
23.0
i ck a
74 FSR input (wl) high before SCKR falling edge
75 FSR input hold time after SCKR falling edge
76 Flags input setup before SCKR falling edge
77 Flags input hold time after SCKR falling edge
1.0
—
—
x ck
23.0
i ck a
3.0
0.0
—
—
x ck
i ck a
0.0
—
—
x ck
19.0
i ck s
6.0
0.0
—
—
x ck
i ck s
46
DSP56371 Technical Data
Freescale Semiconductor
FREESCALE [ Freescale ]
