Reset, Stop, Mode Select, and Interrupt Timing
11
Reset, Stop, Mode Select, and Interrupt Timing
Table 19. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all output pins at
reset value3
—
—
11
ns
11
Required RESET duration4
• Power on, external clock generator, PLL
disabled
2 x TC
2 x TC
11.1
11.1
—
--
ns
ns
• Power on, external clock generator, PLL
enabled
12
13
Syn reset setup time from RESET
• Maximum
TC
—
5.5
—
ns
Syn reset de assert delay time
• Minimum
• Maximum(PLL enabled)
2× TC
11.1
5.0
ns
(2xTC)+TLOCK
ms
14
15
16
Mode select setup time
Mode select hold time
10.0
10.0
11.1
—
—
—
ns
ns
ns
Minimum edge-triggered interrupt request
assertion width
2 xTC
2 xTC
17
11.1
60.0
—
ns
ns
Minimum edge-triggered interrupt request
deassertion width
18
19
Delay from interrupt trigger to interrupt code
execution.
10 xTC + 5
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)2, 3
• PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
9+(128K× TC)
25× TC
704
138
—
—
us
ns
• PLL is active during Stop and Stop delay is
not enabled
(OMR Bit 6 = 1)
• PLL is not active during Stop and Stop delay
is enabled (OMR Bit 6 = 0)
9+(128KxTC)+Tlock
(25 x TC)+Tlock
10 x TC + 3.0
5.7
5
ms
ms
ns
• PLL is not active during Stop and Stop delay
is not enabled (OMR Bit 6 = 1)
20
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer
output valid caused by first interrupt
instruction execution
59.0
36
DSP56371 Technical Data
Freescale Semiconductor
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