Serial Host Interface SPI Protocol Timing
12
Serial Host Interface SPI Protocol Timing
Table 20. Serial Host Interface SPI Protocol Timing
No.
23
Characteristics1
Minimum serial clock cycle = tSPICC(min)
Serial clock high period
Mode
Master
Master
Slave
Min
79.0
29.5
25.8
29.5
25.8
—
Max
—
Unit
ns
24
—
ns
—
ns
25
26
27
Serial clock low period
Serial clock rise/fall time
Master
Slave
—
ns
—
ns
Master
Slave
10
10
ns
—
ns
SS assertion to first SCK edge
CPHA = 0
Slave
34.4
—
ns
CPHA = 1
Slave
Slave
10
12
0
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
28
29
30
31
32
33
Last SCK edge to SS not asserted
Data input valid to SCK edge (data input set-up time)
SCK last sampling edge to data input not valid
SS assertion to data out active
Master/Slave
Master/Slave
Slave
22.4
5
SS deassertion to data high impedance2
Slave
—
SCK edge to data out valid
(data out delay time)
Master/Slave
—
100
34
35
SCK edge to data out not valid
(data out hold time)
Master/Slave
Slave
21.4
—
—
ns
ns
SS assertion to data out valid
(CPHA = 0)
15.0
36
37
First SCK sampling edge to HREQ output deassertion
Slave
Slave
50
—
—
ns
ns
Last SCK sampling edge to HREQ output not deasserted
(CPHA = 1)
52.2
38
39
40
41
SS deassertion to HREQ output not deasserted (CPHA = 0)
SS deassertion pulse width (CPHA = 0)
Slave
Slave
46.6
12.7
—
—
—
—
—
ns
ns
ns
ns
HREQ in assertion to first SCK edge
Master
Master
HREQ in deassertion to last SCK sampling edge (HREQ in
set-up time) (CPHA = 1)
0
42
First SCK edge to HREQ in not asserted
(HREQ in hold time)
Master
Master
0
—
ns
ns
43
HREQ assertion width
Notes:
1. VCORE_VDD = 1.2 5 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
2. Periodically sampled, not 100% tested
Freescale Semiconductor
DSP56371 Technical Data
39
FREESCALE [ Freescale ]
