Specifications
Table 2-22. ESSI Timings (Continued)
80 MHz
100 MHz
Min Max
Cond-
ition6
No.
Characteristics4, 5, 7
Symbol
Expression
Unit
Min
Max
445 Flags input hold time after RXC falling edge
446 TXC rising edge to FST out (bl) high
447 TXC rising edge to FST out (bl) low
6.0
0.0
—
—
6.0
0.0
—
—
x ck
i ck s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
29.0
15.0
—
—
29.0
15.0
x ck
i ck
—
—
31.0
17.0
—
—
31.0
17.0
x ck
i ck
2
448 TXC rising edge to FST out (wr) high
—
—
31.0
17.0
—
—
31.0
17.0
x ck
i ck
2
449 TXC rising edge to FST out (wr) low
—
—
33.0
19.0
—
—
33.0
19.0
x ck
i ck
450 TXC rising edge to FST out (wl) high
451 TXC rising edge to FST out (wl) low
—
—
30.0
16.0
—
—
30.0
16.0
x ck
i ck
—
—
31.0
17.0
—
—
31.0
17.0
x ck
i ck
452 TXC rising edge to data out enable from high
impedance
—
—
31.0
17.0
—
—
31.0
17.0
x ck
i ck
453 TXC rising edge to Transmitter #0 drive enable
assertion
—
—
34.0
20.0
—
—
34.0
20.0
x ck
i ck
8
454 TXC rising edge to data out valid
—
—
20.0
10.0
—
—
20.0
10.0
x ck
i ck
3
455 TXC rising edge to data out high impedance
—
—
31.0
16.0
—
—
31.0
16.0
x ck
i ck
456 TXC rising edge to Transmitter #0 drive enable
—
—
34.0
20.0
—
—
34.0
20.0
x ck
i ck
3
deassertion
457 FST input (bl, wr) setup time before TXC falling
2.0
21.0
—
—
2.0
21.0
—
—
x ck
i ck
2
edge
458 FST input (wl) to data out enable from high
impedance
—
—
27.0
—
—
27.0
—
459 FST input (wl) to Transmitter #0 drive enable
assertion
31.0
31.0
—
460 FST input (wl) setup time before TXC falling edge
461 FST input hold time after TXC falling edge
462 Flag output valid after TXC rising edge
2.5
21.0
—
—
2.5
21.0
—
—
x ck
i ck
4.0
0.0
—
—
4.0
0.0
—
—
x ck
i ck
—
—
32.0
18.0
—
—
32.0
18.0
x ck
i ck
DSP56301 Technical Data, Rev. 10
2-44
Freescale Semiconductor
FREESCALE [ Freescale ]
