AC Electrical Characteristics
POWER
HCLK
357
356
HRST
358
PCI Signals
Figure 2-37. PCI Reset Timing
Table 2-21. SCI Timing
2.5.7 SCI Timing
80 MHz
100 MHz
No.
Characteristics1
Symbol
Expression
Unit
Min Max Min Max
2
400 Synchronous clock cycle
401 Clock low period
t
8 × T
100.0
40.0
40.0
14.3
—
—
—
—
80.0
30.0
30.0
8.0
—
—
—
—
ns
ns
ns
ns
SCC
C
t
t
/2 − 10.0
/2 − 10.0
SCC
402 Clock high period
SCC
403 Output data setup to clock falling edge (internal
clock)
t
/4 + 0.5 × T −17.0
SCC
C
404 Output data hold after clock rising edge (internal
clock)
t
/4 − 0.5 × T
18.8
56.3
—
—
—
15.0
50.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
SCC
C
405 Input data setup time before clock rising edge
(internal clock)
t
/4 + 0.5 × T + 25.0
SCC
C
406 Input data not valid before clock rising edge
(internal clock)
t
/4 + 0.5 × T − 5.5
25.8
32.0
—
19.5
32.0
—
SCC
C
407 Clock falling edge to output data valid (external
clock)
—
—
408 Output data hold after clock rising edge (external
clock)
T
+ 8.0
20.5
0.0
9.0
18.0
0.0
9.0
C
409 Input data setup time before clock rising edge
(external clock)
—
—
410 Input data hold time after clock rising edge (external
clock)
—
—
3
411 Asynchronous clock cycle
412 Clock low period
t
64 × T
800.0
390.0
390.0
370.0
—
—
—
—
640.0
310.0
310.0
290.0
—
—
—
—
ns
ns
ns
ns
ACC
C
t
t
t
/2 − 10.0
/2 − 10.0
/2 − 30.0
ACC
ACC
ACC
413 Clock high period
414 Output data setup to clock rising edge (internal
clock)
415
Output data hold after clock rising edge (internal
clock)
t
/2 − 30.0
370.0
—
290.0
—
ns
ACC
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-41
FREESCALE [ Freescale ]
