AC Electrical Characteristics
411
413
415
412
414
1X SCLK
(Output)
TXD
Data Valid
Figure 2-39. SCI Asynchronous Mode Timing
2.5.8 ESSI0/ESSI1 Timing
Table 2-22. ESSI Timings
80 MHz
100 MHz
Cond-
Unit
No.
Characteristics4, 5, 7
Symbol
Expression
ition6
Min
Max
Min
Max
1
430 Clock cycle
t
3 × T
50.0
37.5
—
—
30.0
40.0
—
—
x ck
i ck
ns
SSICC
C
4 × T
C
431 Clock high period
For internal clock
2 × T − 10.0
15.0
18.8
—
—
10.0
15.0
—
—
ns
ns
C
For external clock
1.5 × T
C
432 Clock low period
For internal clock
2 × T − 10.0
15.0
18.8
—
—
10.0
15.0
—
—
ns
ns
C
For external clock
1.5 × T
C
433 RXC rising edge to FSR out (bl) high
434 RXC rising edge to FSR out (bl) low
435 RXC rising edge to FSR out (wr) high
—
—
37.0
22.0
—
—
37.0
22.0
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
37.0
22.0
—
—
37.0
22.0
x ck
i ck a
2
—
—
39.0
24.0
—
—
39.0
24.0
x ck
i ck a
2
436 RXC rising edge to FSR out (wr) low
—
—
39.0
24.0
—
—
39.0
24.0
x ck
i ck a
437 RXC rising edge to FSR out (wl) high
438 RXC rising edge to FSR out (wl) low
—
—
36.0
21.0
—
—
36.0
21.0
x ck
i ck a
—
—
37.0
22.0
—
—
37.0
22.0
x ck
i ck a
439 Data in setup time before RXC (SCK in
Synchronous mode) falling edge
10.0
19.0
—
—
10.0
19.0
—
—
x ck
i ck
440 Data in hold time after RXC falling edge
441 FSR input (bl, wr) high before RXC falling edge
442 FSR input (wl) high before RXC falling edge
443 FSR input hold time after RXC falling edge
444 Flags input setup before RXC falling edge
5.0
3.0
—
—
5.0
3.0
—
—
x ck
i ck
2
1.0
23.0
—
—
1.0
23.0
—
—
x ck
i ck a
3.5
23.0
—
—
3.5
23.0
—
—
x ck
i ck a
3.0
0.0
—
—
3.0
0.0
—
—
x ck
i ck a
5.5
19.0
—
—
5.5
19.0
—
—
x ck
i ck s
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-43
FREESCALE [ Freescale ]
