AC Electrical Characteristics
2.5.5.1 SRAM Timing
Table 2-8. SRAM Read and Write Accesses3,6
80 MHz
100 MHz
Unit
No.
Characteristics
Symbol
Expression1
Min
Max
Min
Max
100 Address valid and AA
t
, t
(WS + 1) × T − 4.0 [1 ≤ WS ≤ 3]
21.0
71.0
133.5
—
—
—
16.0
56.0
106.0
—
—
—
ns
ns
ns
RC WC
C
2
assertion pulse width
(WS + 2) × T − 4.0 [4 ≤ WS ≤ 7]
C
(WS + 3) × T − 4.0 [WS ≥ 8]
C
101 Address and AA valid to
WR assertion
t
0.25 × T − 2.0 [WS = 1]
1.1
7.4
13.6
—
—
—
0.5
5.5
10.5
—
—
—
ns
ns
ns
AS
C
0.75 × T − 2.0 [2 ≤ WS ≤ 3]
C
1.25 × T − 2.0 [WS ≥ 4]
C
102 WR assertion pulse width
t
1.5 × T − 4.0 [WS = 1]
14.8
21.0
39.8
—
—
—
11.0
16.0
31.0
—
—
—
ns
ns
ns
WP
C
WS × T − 4.0 [2 ≤ WS ≤ 3]
C
(WS − 0.5) × T − 4.0 [WS ≥ 4]
C
103 WR deassertion to
address not valid
t
0.25 × T − 2.0 [1 ≤ WS ≤ 3]
1.1
11.6
24.1
—
—
—
0.5
8.5
18.5
—
—
—
ns
ns
ns
WR
C
1.25 × T − 4.0 [4 ≤ WS ≤ 7]
C
2.25 × T − 4.0 [WS ≥ 8]
C
104 Address and AA valid to
input data valid
t
, t
(WS + 0.75) × T − 5.0 [WS ≥ 1]
—
—
16.9
10.6
—
—
—
12.5
7.5
—
ns
ns
ns
ns
ns
AA AC
C
105 RD assertion to input data
valid
t
(WS + 0.25) × T − 5.0 [WS ≥ 1]
OE
C
106 RD deassertion to data not
valid (data hold time)
t
0.0
17.9
6.4
0.0
13.5
4.5
OHZ
107 Address valid to WR
t
(WS + 0.75) × T − 4.0 [WS ≥ 1]
—
—
AW
C
2
deassertion
108 Data valid to WR
deassertion (data setup
time)
t
(t
)
(WS − 0.25) × T − 3.0 [WS ≥ 1]
—
—
DS DW
C
109 Data hold time from WR
deassertion
t
0.25 × T − 2.0 [1 ≤ WS ≤ 3]
1.1
13.6
26.1
—
—
—
0.5
10.5
20.5
—
—
—
ns
ns
ns
DH
C
1.25 × T − 2.0 [4 ≤ WS ≤ 7]
C
2.25 × T − 2.0 [WS ≥ 8]
C
110 WR assertion to data
active
0.75 × T − 3.7 [WS = 1]
5.7
–0.6
–6.8
—
—
—
3.8
–1.2
–6.2
—
—
—
ns
ns
ns
C
0.25 × T − 3.7 [2 ≤ WS ≤ 3]
C
−0.25 × T − 3.7 [WS ≥ 4]
C
111 WR deassertion to data
high impedance
0.25 × T + 0.2 [1 ≤ WS ≤ 3]
—
—
—
3.3
15.8
28.3
—
—
—
2.7
12.7
22.7
ns
ns
ns
C
1.25 × T + 0.2 [4 ≤ WS ≤ 7]
C
2.25 × T + 0.2 [WS ≥ 8]
C
112 Previous RD deassertion
to data active (write)
1.25 × T − 4.0 [1 ≤ WS ≤ 3]
11.6
24.1
36.6
—
—
—
8.5
18.5
28.5
—
—
—
ns
ns
ns
C
2.25 × T − 4.0 [4 ≤ WS ≤ 7]
C
3.25 × T − 4.0 [WS ≥ 8]
C
113 RD deassertion time
114 WR deassertion time
0.75 × T − 4.0 [1 ≤ WS ≤ 3]
5.4
17.9
30.4
—
—
—
3.5
13.5
23.5
—
—
—
ns
ns
ns
C
1.75 × T − 4.0 [4 ≤ WS ≤ 7]
C
2.75 × T − 4.0 [WS ≥ 8]
C
0.5 × T − 4.0 [WS = 1]
2.3
8.5
27.3
39.8
—
—
—
—
1.0
6.0
21.0
31.0
—
—
—
—
ns
ns
ns
ns
C
T
− 4.0 [2 ≤ WS ≤ 3]
C
2.5 × T − 4.0 [4 ≤ WS ≤ 7]
C
3.5 × T − 4.0 [WS ≥ 8]
C
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-13
FREESCALE [ Freescale ]
