AC Electrical Characteristics
2.5.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
80 MHz
100 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
3
8
9
Delay from RESET assertion to all pins at reset value
—
—
26.0
—
26.0
ns
4
Required RESET duration
•
•
•
•
•
•
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
50 × ET
1000 × ET
75000 × ET
75000 × ET
625.0
12.5
1.0
1.0
31.3
31.3
—
—
—
—
—
—
500.0
10.0
0.75
0.75
25.0
25.0
—
—
—
—
—
—
ns
μs
ms
ms
ns
C
C
C
C
2.5 × T
C
2.5 × T
ns
C
10 Delay from asynchronous RESET deassertion to first
5
external address output (internal reset deassertion)
•
•
Minimum
Maximum
3.25 × T + 2.0
42.6
—
—
263.1
34.5
—
—
212.5
ns
ns
C
20.25 T + 10.0
C
11 Synchronous reset setup time from RESET deassertion to
CLKOUT Transition 1
T
C
•
•
Minimum
Maximum
7.4
—
—
12.5
5.9
—
—
10.0
ns
ns
12 Synchronous reset deasserted, delay time from the
CLKOUT Transition 1 to the first external address output
•
•
Minimum
Maximum
3.25 × T + 1.0
41.6
—
—
258.1
33.5
—
—
207.5
ns
ns
C
20.25 × T + 1.0
C
13 Mode select setup time
30.0
0.0
—
—
30.0
0.0
—
—
ns
ns
14
Mode select hold time
15
16
Minimum edge-triggered interrupt request assertion width
8.25
—
6.6
—
ns
Minimum edge-triggered interrupt request deassertion
width
8.25
—
7.1
—
ns
17
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
•
•
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
4.25 × T + 2.0
55.1
92.6
—
—
44.5
74.5
—
—
ns
ns
C
7.25 × T + 2.0
C
18
19
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first
interrupt instruction execution
10 × T + 5.0
130.0
—
105.0
—
ns
C
Delay from address output valid caused by first interrupt 80 MHz:
—
Note 8
ns
instruction execute to interrupt request deassertion for
level sensitive fast interrupts
3.75 × T + WS × T – 12.4
100 MHz:
C
C
1
—
Note 8 ns
ns
3.75 × T + WS × T – 10.94
C
C
20
Delay from RD assertion to interrupt request deassertion 80 MHz:
—
Note 8
1
for level sensitive fast interrupts
3.25 × T + WS × T – 12.4
C
C
100 MHz:
3.25 × T + WS × T – 10.94
—
Note 8 ns
C
C
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-7
FREESCALE [ Freescale ]
