AC Electrical Characteristics
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
80 MHz
100 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
28 DMA Request Rate
•
•
•
•
Data read from HI32, ESSI, SCI
Data write to HI32, ESSI, SCI
Timer
6 × T
—
—
—
—
75.0
87.5
25.0
37.5
—
—
—
—
60.0
70.0
20.0
30.0
ns
ns
ns
ns
C
7 × T
C
2 × T
C
IRQ, NMI (edge trigger)
3 × T
C
29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory (DMA source) access address out valid
4.25 × T + 2.0
55.1
—
44.5
—
ns
C
Notes: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended
when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. This timing depends on several settings:
• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the
Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,
it is not recommended, and these specifications do not guarantee timings for that case.
• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no
stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).
• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the
PCTL Bit 17 and Operating Mode Register Bit 6 settings.
• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion.
• PLC value for PLL disable is 0.
• The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is
C
4096/66 MHz = 62 μs). During the stabilization period, T , T and T is not constant, and their width may vary, so timing may
C
H,
L
vary as well.
3. Periodically sampled and not 100 percent tested.
4. Value depends on clock source:
• For an external clock generator, RESET duration is measured while RESET is asserted, V is valid, and the EXTAL input is
CC
active and valid.
• For an internal oscillator, RESET duration is measured while RESET is asserted and V is valid. The specified timing
CC
reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal
and other components connected to the oscillator and reflects worst case conditions.
• When the V is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
CC
device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5. If PLL does not lose lock.
6.
V
= 3.3 V 0.3 V; T = –40°C to +100°C, C = 50 pF.
CC J L
7. WS = number of wait states (measured in clock cycles, number of T ).
C
8. Use the expression to compute a maximum value.
RESET
V
IH
9
10
8
All Pins
Reset Value
First Fetch
A[0–23]
Figure 2-3. Reset Timing
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-9
FREESCALE [ Freescale ]
