Specifications
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
80 MHz
100 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
21 Delay from WR assertion to interrupt request deassertion
1
for level sensitive fast interrupts
7
•
•
•
•
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS ≥ 4
80 MHz:
—
Note 8
ns
ns
ns
ns
ns
ns
ns
ns
(WS + 3.5) × T – 12.4
C
100 MHz:
—
—
—
Note 8
Note 8
Note 8
Note 8
(WS + 3.5) × T – 10.94
C
80 MHz:
—
—
—
Note 8
Note 8
Note 8
(WS + 3.5) × T – 12.4
C
100 MHz:
(WS + 3.5) × T – 10.94
C
80 MHz:
(WS + 3) × T – 12.4
C
100 MHz:
(WS + 3) × T – 10.94
C
80 MHz:
(WS + 2.5) × T – 12.4
C
100 MHz:
—
(WS + 2.5) × T – 10.94
C
22 Synchronous interrupt setup time from IRQA, IRQB,
IRQC, IRQD, NMI assertion to the CLKOUT Transition 2
7.4
T
5.9
T
ns
C
C
23 Synchronous interrupt delay time from the CLKOUT
Transition 2 to the first external address output valid
caused by the first instruction fetch after coming out of
Wait Processing state
8.25 × T + 1.0
116.6
—
—
314.4
83.5
—
—
252.5
ns
ns
C
•
•
Minimum
Maximum
24.75 × T + 5.0
C
24 Duration for IRQA assertion to recover from Stop state
7.4
1.6
—
5.9
1.3
—
ns
25 Delay from IRQA assertion to fetch of first instruction
2, 3
(when exiting Stop)
•
•
•
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is enabled (Operating Mode Register Bit 6
= 0)
PLC × ET × PDF + (128 K −
17.0
13.6
ms
C
PLC/2) × T
C
PLC × ET × PDF + (23.75
290.6 ns 15.4 ms 232.5
ns
12.3
ms
C
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is not enabled (Operating Mode Register
Bit 6 = 1)
0.5) × T
C
(9.25 ± 0.5) × TC
109.4
121.9
87.5
97.5
ns
PLL is active during Stop (PCTL Bit 17 = 1) (Implies
No Stop Delay)
26 Duration of level sensitive IRQA assertion to ensure
2, 3
interrupt service (when exiting Stop)
•
•
•
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is enabled (Operating Mode Register Bit 6
= 0)
PLC × ET × PDF + (128K −
17.0
15.4
68.8
—
—
—
13.6
12.3
55.0
—
—
—
ms
ms
ns
C
PLC/2) × T
C
PLC × ET × PDF +
C
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is not enabled (Operating Mode Register
Bit 6 = 1)
(20.5 0.5) × T
C
5.5 × T
C
PLL is active during Stop (PCTL Bit 17 = 1) (implies no
Stop delay)
27 Interrupt Request Rate
•
•
•
•
HI32, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
12 × T
—
—
—
—
150.0
100.0
100.0
150.0
—
—
—
—
120.0
80.0
80.0
ns
ns
ns
ns
C
8 × T
C
8 × T
C
12 × T
120.0
C
DSP56301 Technical Data, Rev. 10
2-8
Freescale Semiconductor
FREESCALE [ Freescale ]
