Specifications
2.5 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.3 V
IL
and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
IH
Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with
respect to the 50 percent point of the respective input signal’s transition.
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
MHz and rated speed.
All specifications for the high impedance state are guaranteed by design.
2.5.1 Internal Clocks
Table 2-4. Internal Clocks, CLKOUT
Expression1, 2
Characteristics
Symbol
Min
Typ
Max
Internal operation frequency and CLKOUT with PLL enabled
f
f
—
(Ef × MF)/
(PDF × DF)
—
Internal operation frequency and CLKOUT with PLL disabled
Internal clock and CLKOUT high period
—
Ef/2
—
•
•
With PLL disabled
With PLL enabled and MF ≤ 4
T
—
ET
—
—
H
C
0.49 × ET
×
0.51 × ET ×
C
C
PDF × DF/MF
PDF × DF/MF
0.53 × ET
•
With PLL enabled and MF > 4
0.47 × ET
×
—
×
C
C
PDF × DF/MF
PDF × DF/MF
Internal clock and CLKOUT low period
•
•
With PLL disabled
With PLL enabled and MF ≤ 4
T
—
ET
—
—
L
C
0.49 × ET
×
0.51 × ET ×
C
C
PDF × DF/MF
PDF × DF/MF
0.53 × ET
•
With PLL enabled and MF > 4
0.47 × ET
×
—
×
C
C
PDF × DF/MF
PDF × DF/MF
Internal clock and CLKOUT cycle time with PLL enabled
T
—
ET
PDF ×
DF/MF
×
C
—
C
C
Internal clock and CLKOUT cycle time with PLL disabled
Instruction cycle time
T
—
2 × ET
—
C
I
—
T
—
CYC
C
Notes: 1. DF = Division Factor; Ef = External frequency; ET = External clock cycle = 1/Ef;
C
MF = Multiplication Factor; PDF = Predivision Factor; T = Internal clock cycle
C
2. See the PLL and Clock Generator section in the DSP56300 Family Manual for details on the PLL.
DSP56301 Technical Data, Rev. 10
2-4
Freescale Semiconductor
FREESCALE [ Freescale ]
