Freescale Semiconductor, Inc.
MCF5206e Overview
— Master or slave modes supporting multiple masters
— Automatic interrupt generation with programmable level
System interface
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— Glueless bus interface to 8 bit, 16 bit, and 32 bit DRAM, SRAM, ROM, and I/O devices
— Eight programmable chip selects and programmable wait states and port sizes allowing
external bus masters to access chip selects
— Programmable external interrupts
— 8-bit general-purpose I/O interface
— System protection
– 16-bit software watchdog timer with prescaler
– Double bus fault monitor
– Bus timeout monitor
– Spurious interrupt monitor
– Programmable interrupt controller (low interrupt latency, 3 external interrupt inputs, and
programmable interrupt priority and autovector generator)
— IEEE 1149.1 test (JTAG) support
System debug interface
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— Real-time trace
— Background debug mode (BDM)
Fully static 3.3-volt operation with 5-volt tolerant inputs
160-pin QFP package; pin-compatible with MCF5206
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1.1.2 ColdFire Version 2 Core
The ColdFire processor core consists of two independent, decoupled pipeline structures that maximize
performance while minimizing core size. The instruction fetch pipeline (IFP) is a two-stage pipeline for
prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand
execution pipeline (OEP), which decodes the instruction, fetches the required operands and then executes
the required function. The IFP and OEP pipelines are decoupled by an instruction buffer that serves as a
FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing
time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional
RISC datapath with a dual-read-ported register file feeding an arithmetic/logic unit.
1.1.3 Instruction Cache
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock. The MCF5206e processor uses a 4-Kbyte, direct-mapped instruction cache to achieve 50
MIPS at 54 MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an
address tag and a valid bit. The instruction cache also includes a bursting interface for 32-bit, 16-bit, and
8-bit port sizes to fill cache lines quickly.
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MCF5206e Integrated ColdFire® Microprocessor Product Brief
MOTOROLA
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