Freescale Semiconductor, Inc.
Product Brief
MCF5206EPB/D
Rev.2.1, 3/2002
MCF5206e Integrated
®
ColdFire Microprocessor
Product Brief
®
The MCF5206e integrated microprocessor combines a ColdFire core with several peripheral
functions such as a DRAM controller, timers, parallel and serial interfaces, and system
integration. This device is an enhanced version of the MCF5206, which is in production today.
Not only does the MCF5206e provide a performance upgrade to the MCF5206 due to the
increased 4-Kbyte I-cache, 8-Kbyte SRAM and increased frequency, but this device also
integrates an additional multiply accumulate (MAC) unit, hardware divide, and two-channel
DMA to the device while maintaining pin compatibility with the MCF5206.
The revolutionary ColdFire architecture gives cost-sensitive, high-volume markets new levels
of price and performance. Based upon the concept of variable-length RISC technology, the
ColdFire core combines the architectural simplicity of conventional 32-bit RISC with a
memory-saving, variable-length instruction set. In defining the ColdFire architecture for
embedded processing applications, Motorola incorporated RISC architecture for peak
performance and a simplified version of the variable-length instruction set found in the
M68000 family for code density.
By using a variable-length instruction set architecture, embedded processor designers using
ColdFire processors will enjoy significant system-level advantages over conventional
fixed-length RISC architectures. The denser binary code for ColdFire uses less memory than
fixed-length instruction processors available. This improved code density means more
efficient system memory usage for a given application, and allows for slower, less costly
memory to help achieve a target price/performance level for embedded processing
applications.
The MCF5206e Version 2 core delivers enhanced performance while maintaining low system
costs. The addition of a MAC module and hardware divide to the core increases performance
of complex arithmetic functions normally used in DSP applications. To speed program
execution, the on chip instruction cache and SRAM provides one-cycle access to critical code
and data. The MCF5206e processor greatly reduces the time required for system design and
implementation by packaging common system functions on chip and providing glueless
interfaces to 8 bit, 16 bit and 32 bit DRAM, SRAM, ROM and I/O devices.
The integrated peripheral functions provide high performance and flexibility. The DRAM
controller supports up to 512 Mbytes of DRAM. The MCF5206e processor supports both fast
page-mode and extended-data-out DRAMs. The DMA controller provides two fully
programmable channels that support both single and dual addressing modes. The serial
2
1
interfaces consists of two independent UARTs and a separate I C-compatible Motorola bus
(M-Bus interface). Two 16-bit general-purpose multimode timers provide separate input and
output signals. For system protection, the processor includes a programmable 16-bit software
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