Freescale Semiconductor, Inc.
MCF5206e Overview
— 16 user-visible 32-bit wide registers
— Supervisor and user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high level language constructs
— 50 MIPS at 54 MHz
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Multiply accumulate
— High speed, complex arithmetic functions for signal processing applications
— Single clock issue rate with 3-stage execution pipeline
— One MAC cycle for 16x16 and 32x32 multiplies, all with 32-bit accumulate
— Four-Kbyte direct-mapped instruction cache
— Eight-Kbyte on-chip SRAM that provides one-cycle access to critical code and data
DRAM controller
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— Programmable refresh timer provides CAS before RAS refresh
— Support for 2 separate memory banks
— Support for fast page mode DRAMs and extended-data-out (EDO) DRAMs
— External bus master access
DMA controller
— Two fully programmable channels with external request pins supporting dual-address and
single address transfers with 32-bit capability
— Two address pointers per channel that can increment or remain constant
— 16-bit transfer counter per channel
— Operand packing and unpacking
— Auto-alignment transfers for efficient block movement
— Bursting and cycle stealing
— Two clock-cycle internal access
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Two universal synchronous/asynchronous receiver/transmitters (UARTs)
— Full duplex operation
— Baud-rate generator
— Modem control signals (CTS, RTS)
— Processor-interrupt capability
Dual 16-bit general-purpose multimode timers
— 8-bit prescaler
— Timer input and output pins
— 12 ns resolution with 54 MHz system clock
— Processor interrupt capability
Motorola bus (M-Bus) module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads
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— Compatible with industry-standard I C bus
MOTOROLA
MCF5206e Integrated ColdFire® Microprocessor Product Brief
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