欢迎访问ic37.com |
会员登录 免费注册
发布采购

C5EC3EARCH-RM/D 参数 Datasheet PDF下载

C5EC3EARCH-RM/D图片预览
型号: C5EC3EARCH-RM/D
PDF下载: 下载PDF文件 查看货源
内容描述: C- 3E网络处理器芯片版本A1 [C-3e NETWORK PROCESSOR SILICON REVISION A1]
分类和应用:
文件页数/大小: 114 页 / 2056 K
品牌: FREESCALE [ Freescale ]
 浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第75页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第76页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第77页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第78页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第80页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第81页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第82页浏览型号C5EC3EARCH-RM/D的Datasheet PDF文件第83页  
AC Timing Specifications  
79  
AC Timing Specifications  
AC timing specifications consist of input requirements and output responses. The input  
requirements include setup and hold times, pulse widths, and high and low times. The  
output responses include delays from clock to signal. The AC timing specifications are  
defined separately for each interface to the C-3e NP.  
See Figure 12. Output timing specifications for LVTTL pins are given with a 20pF load on  
the output. Other loads can be simulated with the IBIS model available from Motorola.  
The LVPECL driver is specified into a 50load terminated to a (VDD33 - 2V) reference.  
Figure 12 Test Loading Conditions  
LVTTL  
DUT  
20pF  
VDD33  
+2V  
LVPECL  
DUT  
50  
03  
 复制成功!