80
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Clock Timing The system clock timing is shown in Figure 13 and described in Table 37.
Specifications
Figure 13 System Clock Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 1
SCLK
SCLKX
T
sc
T
sh
T
sl
CCLKn
T
ccN
T
cch
T
ccl
Table 37 System Clock Timing Description
SYMBOL
Tsc
PARAMETER
MIN
TYP
MAX
UNIT COMMENT
System Cycle Time 3.76
Sys Clk High Pulse 45
ns
180MHz core clock
Tsh
55
55
Duty cycle*
Tsl
Sys Clk Low Pulse
CCLK0 Cycle Time
CCLK1 Cycle Time
CCLK2 Cycle Time
CCLK3 Cycle Time
45
Duty cycle*
Tcc0
Tcc1
Tcc2
Tcc3
Tcch
Tccl
6.43
6.43
6.43
6.43
ns
ns
ns
ns
†
†
†
†
CCLKm High Time 40%
CCLKm Low Time 40%
60%
60%
% cycle pulse is high
% cycle pulse is low
*
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX
The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one
†
or more CCLKn inputs for other frequencies; contact your Motorola representative for more information.
C3EN
FREESCALE [ Freescale ]
