AC Timing Specifications
83
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in
Table 40. The TBI interface timing is shown in Figure 16 and described in Table 41.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
GMII / TBI Tx
Cycle 1
CPn_0 (TCLK)
T
cgt
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
T
cgo
Cycle 1
Cycle 2
Cycle 3
MII Tx
MII CPn_1 (TCLKI)
T
cmt
MII CPn_2-6 (Tx)
T
cmo
TBI Rx
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
T
ctr
T
ctd
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
T
cts
T
cth
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
GMII/MII Rx
CPn+2_1 (RCLK)
T
cgr
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
T
T
cgh
cgs
03
FREESCALE [ Freescale ]
